HBM Market Statistics 2026
By Axis Intelligence Research
Co-author: Sarah Mitchell | Last updated: August 3, 2026 | License: CC BY 4.0
Three companies make every high-bandwidth memory stack shipped into an AI accelerator, and in their most recent reported quarters all three earned a higher operating margin than NVIDIA. Axis Intelligence Research puts the unweighted average at 75.6% against NVIDIA’s 65.6% — a ten-point premium held by the suppliers, not the chip designer.
Quick Answer
Micron, SK hynix and Samsung are the only volume producers of HBM. In their latest reported quarters, their operating margins were 80.4%, 76.3% and 70.0% respectively (Samsung figure covers the whole Device Solutions division). Axis Intelligence Research calculates a Memory Margin Premium of +10.0 percentage points over NVIDIA’s 65.6% and +15.2 points over TSMC’s 60.3%. All three shipped HBM4 in volume during the first half of calendar 2026; only Micron has disclosed a hard HBM4 revenue number, and it is more than $1 billion.
Key Findings
- Axis Intelligence Research finds that the three HBM producers averaged a 75.6% operating margin in their most recent reported quarters, versus 65.6% at NVIDIA and 60.3% at TSMC — the first period in which the memory layer of the AI stack out-earned both the accelerator designer and the foundry.
- Micron reported $41.46 billion of revenue in its fiscal third quarter ended May 28, 2026, up 346% year over year, with DRAM alone at a record $31.3 billion — 75.5% of company revenue, per Axis Intelligence Research’s calculation from Micron’s disclosed segment data.
- SK hynix reported 79.32 trillion won of revenue and 60.54 trillion won of operating profit in Q2 2026, a 76% operating margin, and crossed 100 trillion won of first-half revenue for the first time in company history.
- Samsung’s Device Solutions division posted 127.5 trillion won of revenue and 89.2 trillion won of operating profit in Q2 2026 — 99.7% of the entire company’s operating profit, by Axis Intelligence Research’s calculation, while the mobile division ran a loss.
- Axis Intelligence Research finds that none of the three HBM suppliers discloses HBM revenue as a reported line item, which means every published “HBM market share” figure in circulation is a third-party estimate rather than an audited number.
How Big Is the HBM Market in 2026?
There is no honest single answer, and the reason matters more than the estimate.
HBM is manufactured by exactly three companies. None of them reports it as a segment. Micron folds HBM into its Cloud Memory Business Unit, SK hynix reports DRAM in aggregate, and Samsung reports a Memory Business inside a Device Solutions division that also contains foundry and System LSI. The market-size numbers that circulate in trade press are modelled from bit shipments and estimated pricing by research firms — they are not drawn from any filing.
Axis Intelligence Research will not publish an HBM market-size figure we cannot trace to a disclosure. What we can publish, and what no one else assembles in one place, is the full set of audited numbers the three suppliers do report, plus the two AI-chain reference points that make those numbers legible.
Reported revenue and operating results, latest quarter
| Company | Period | Revenue | Operating income | Operating margin | Source |
|---|---|---|---|---|---|
| Micron Technology | FQ3 FY2026 (ended May 28, 2026) | $41.456B | $33.318B | 80.4% | Micron Q3 FY26 press release |
| SK hynix | Q2 2026 (ended Jun 30, 2026) | ₩79,318.7B | ₩60,542.6B | 76.3% | SK hynix 2Q26 results |
| Samsung Electronics (DS Division) | Q2 2026 (ended Jun 30, 2026) | ₩127.5T | ₩89.2T | 70.0% | Samsung Q2 2026 results |
| NVIDIA (reference) | Q1 FY2027 (ended Apr 26, 2026) | $81.615B | $53.536B | 65.6% | NVIDIA Q1 FY27 press release |
| TSMC (reference) | Q2 2026 (ended Jun 30, 2026) | NT$1,270.38B | NT$766.60B | 60.3% | TSMC Form 6-K, SEC |
Sources: Micron FQ3 FY2026 results; SK hynix 2Q26 results; Samsung Electronics Q2 2026 results; NVIDIA Q1 FY2027 results; TSMC Q2 2026 Form 6-K filed with the SEC. Margins for Micron, NVIDIA and TSMC computed by Axis Intelligence Research from reported revenue and operating income; SK hynix and Samsung margins as reported and as computed. Reporting periods are not identical — see Methodology.
Sarah Mitchell’s read: For two years the assumption in every AI infrastructure deck was that the accelerator designer captures the economics and memory is a component you buy. That ordering has inverted, and the filings say so plainly. Micron’s fiscal Q3 gross margin, as filed, was 84.6%. That is not a component supplier’s number. It is what happens when demand for a physically constrained input runs ahead of the wafer capacity that produces it, and when three suppliers — not thirty — control the entire output.
Which Company Leads the HBM Market? The Share-Estimate Problem
Search interest in “HBM market share” is heavy, and the figure most often quoted is a research-firm estimate placing SK hynix somewhere around half to sixty percent of HBM revenue. Axis Intelligence Research does not restate that number as fact, for a reason worth stating explicitly: no company in this market publishes HBM revenue, so no share figure can be reconciled against a filing.
What is verifiable is disclosure behaviour, and that is a real signal. So Axis Intelligence Research built a scorecard from it.
The Axis HBM4 Disclosure Index (HDI) — baseline reading, August 3, 2026
The HDI scores each supplier on four binary criteria drawn strictly from its most recent public results disclosure. Each criterion carries equal weight (0.25). This is a baseline reading — the first computation of this metric, with no prior history to compare against.
| Criterion (equal weight) | Micron | SK hynix | Samsung |
|---|---|---|---|
| HBM4 confirmed in volume production / mass shipment | Yes | Yes | Yes |
| HBM4E samples confirmed shipped to customers | No | Yes | Yes |
| A quantified HBM4 revenue figure disclosed | Yes | No | No |
| A quantified forward HBM4 ramp disclosed | No | No | Yes |
| HDI score (of 1.00) | 0.50 | 0.50 | 0.75 |
Source: Micron FQ3 FY26 press release and prepared remarks (June 24, 2026); SK hynix 2Q26 results (July 29, 2026); Samsung Electronics Q2 2026 results (July 30, 2026). Compiled by Axis Intelligence Research, as of August 3, 2026.
What the HDI measures and what it does not. It measures how much verifiable information each supplier releases about its HBM4 position. It is not a technology ranking, a yield ranking, or a market-share proxy. A company can lead the market and disclose almost nothing; Samsung’s leading score here reflects that it quantified its HBM4 trajectory — sales expected to more than triple quarter over quarter in Q3, and HBM4 expected to account for well over 60% of HBM revenue in the second half of 2026 — while its competitors described theirs qualitatively.
What each supplier actually disclosed
Micron stated that HBM4 built on 1-beta DRAM is in high-volume shipment for its lead customer’s platform and that qualification samples have gone to multiple end customers. In its fiscal Q3 earnings-call prepared remarks it went further, disclosing the only hard number any supplier has put on the table: it has already shipped over $1 billion in HBM4 revenue, with the HBM4 12-high volume ramp tracking twice as fast as HBM3E 12-high. HBM4E, built on 1-gamma, is in development with volume production expected in calendar 2027.
SK hynix began mass shipments of HBM4 in Q2 2026 and said it will ramp production in the second half. It completed HBM4E sample shipments in the first half. It disclosed no HBM revenue figure and no HBM4 mix percentage.
Samsung scaled up HBM4 sales during Q2 and shipped what it called the industry’s first HBM4E samples to major customers. Its foundry business separately noted that earnings improved on HBM base-die demand — a rare instance of HBM appearing as a named driver in a non-memory segment.
Why Are HBM Prices and Margins So High in 2026?
The answer is in the supply math, and Micron’s management laid it out with unusual candour. Memory bit-supply growth is constrained by greenfield fab expansion, which is slow for reasons that have nothing to do with semiconductors: construction lead times, shortages of skilled trades, permitting, and grid interconnection. Meanwhile each new HBM generation carries a worse trade ratio — the wafer capacity consumed per usable bit rises with every generation, so HBM growth actively cannibalises non-HBM DRAM supply.
Micron’s own outlook is that it has no line of sight to when memory supply catches up with demand, even assuming gradual improvement in 2028. Samsung told the same story from the other side: it expects the market to remain undersupplied through the second half of 2026 despite softening mobile and PC demand, with supply constraints persisting.
The pricing consequence shows up directly in Micron’s own quarterly disclosure: fiscal Q3 DRAM prices rose in the low-60s percentage range sequentially, on bit shipments that grew only in the low single digits. NAND prices rose in the mid-80s percentage range. Those are not cyclical price moves; they are the arithmetic of an allocated market.
The contracts changed shape too
Both Korean suppliers and Micron have moved to multi-year committed supply. Micron has signed 16 strategic customer agreements, typically five-year terms running calendar 2026 through 2030, structured as take-or-pay with binding volume commitments. Fourteen of those sixteen carry cumulative minimum-price revenue of roughly $100 billion over the remaining term, with $22 billion in cash deposits and related financial commitments — approximately $18 billion of it in actual cash deposits. SK hynix has finalised long-term agreements with around ten customers. Samsung said it plans to allocate roughly 60–70% of capacity to long-term contracts.
Sarah Mitchell’s read: This is the part the market has not fully priced. Memory has historically been a spot business with a brutal cycle — capacity arrives, prices collapse, everyone writes down inventory. Take-or-pay agreements with floor pricing and customer cash deposits are a different instrument. They do not abolish the cycle, but they change who absorbs it. When Micron says its floor price “enables a very robust gross margin well above our peak quarterly margins in any past cycle,” that is a statement about the bottom of the next downturn, not the top of this upturn. The claim is worth watching precisely because it has never been tested.
What Is HBM4 and How Much Faster Is It?
HBM4 is the fourth-generation JEDEC standard, published as JESD270-4 in April 2025. The specification defines transfer speeds up to 8 Gb/s across a 2,048-bit interface, for total bandwidth up to 2 TB/s per stack. Independent channels per stack double from 16 in HBM3 to 32, each split into two pseudo-channels. The standard supports 4-, 8-, 12- and 16-high DRAM stack configurations using 24 Gb or 32 Gb dies, and introduces Directed Refresh Management for row-hammer mitigation.
| Parameter | HBM3 | HBM4 (JESD270-4) | Source |
|---|---|---|---|
| Interface width | 1,024-bit | 2,048-bit | JEDEC |
| Peak transfer speed | — | Up to 8 Gb/s per pin | JEDEC |
| Peak bandwidth per stack | — | Up to 2 TB/s | JEDEC |
| Independent channels per stack | 16 | 32 (2 pseudo-channels each) | JEDEC |
| Stack heights supported | — | 4, 8, 12, 16-high | JEDEC |
| Die densities | — | 24 Gb, 32 Gb | JEDEC |
Source: JEDEC Solid State Technology Association, JESD270-4 HBM4 standard announcement, April 16, 2025.
The practical consequence for AI infrastructure is that memory bandwidth, not logic throughput, sets the ceiling on inference performance for large-context workloads. Doubling the interface width is the single largest architectural change in the HBM family since it was standardised.
Is HBM Export-Controlled? What ECCN 3A090.c Actually Covers
Yes, and the control is written in a way that captures the entire product category.
The U.S. Bureau of Industry and Security created ECCN 3A090.c in an interim final rule effective December 2, 2024, published at 89 FR 96790. It controls HBM with a memory bandwidth density greater than 2 gigabytes per second per square millimetre, defined as the bandwidth of the package or stack divided by its footprint area. BIS stated plainly in the rule that all HBM stacks currently in production exceed this threshold. The control applies regardless of whether a device conforms to the JEDEC HBM standards.
The same rule rewrote the definition of an advanced-node DRAM integrated circuit, replacing a half-pitch criterion with two alternatives: a memory cell area below 0.0019 square micrometres, or a memory density above 0.288 gigabits per square millimetre. BIS explained the change directly — the previous half-pitch definition did not capture HBM, because vertical stacking raised density without shrinking half-pitch.
A narrow carve-out exists. License Exception HBM (15 CFR § 740.25) authorises certain shipments of 3A090.c items with bandwidth density below 3.3 GB/s/mm², by exporters headquartered in the U.S. or a Country Group A:5 destination without an ultimate parent in Macau or Country Group D:5, shipped directly to a qualifying packaging site under tracking conditions. A subsequent BIS rule in January 2025 added related due-diligence guidance, including a red flag for items combining more than 50 billion transistors with HBM.
Co-packaged devices where the dominant function is processing fall outside 3A090.c — they are controlled, if at all, under 3A090.a or .b on processing-performance criteria instead.
Sarah Mitchell’s read: The bandwidth-density threshold is the clever part of the drafting. BIS chose density over raw bandwidth specifically so the control could not be defeated by stacking more small parts. Two GB/s/mm² is set below every shipping product, which means the rule is a categorical control dressed as a technical one — and it will stay categorical until someone builds an HBM part deliberately worse than the 2015 state of the art, which no one will.
Where Does the Bottleneck Actually Sit?
Not at the DRAM wafer. HBM stacks have to be co-packaged with logic dies, and that packaging step is concentrated at TSMC. TSMC reported $40.20 billion of Q2 2026 revenue at a 60.3% operating margin and is expanding advanced packaging capacity, but the constraint is physical and multi-year: Micron expects its new Singapore advanced-packaging centre to contribute meaningfully to HBM packaging capacity only from the first half of calendar 2027, and its Idaho ID1 fab reaches first wafer output around mid-2027.
That timing is the most important number in this entire report. Every supply commitment being signed today for 2027 and 2028 delivery is being made against capacity that does not yet exist.
Methodology
Collection. Every figure in this report was retrieved from a primary source document fetched during the production session on August 3, 2026. Sources are the issuing organisations’ own disclosures: Micron’s FQ3 FY2026 press release and prepared remarks, SK hynix’s 2Q26 results, Samsung’s Q2 2026 results, NVIDIA’s Q1 FY2027 results, TSMC’s Q2 2026 Form 6-K on SEC EDGAR, the BIS interim final rule at 89 FR 96790, its January 2025 due-diligence companion rule, and the JEDEC JESD270-4 announcement. Each figure has a corresponding row in the downloadable CSV, including source URL and retrieval date. No figure in this report is drawn from a market-research estimate or a secondary aggregator.
Axis Memory Margin Premium (MMP) — formula, v1.0.
MMP = mean(OM_Micron, OM_SKhynix, OM_SamsungDS) − OM_reference
OM_Micron = 33,318 / 41,456 = 80.37% (FQ3 FY2026, GAAP, USD m)
OM_SKhynix = 60,542.6 / 79,318.7 = 76.33% (Q2 CY2026, K-IFRS, KRW bn)
OM_SamsungDS = 89.2 / 127.5 = 69.96% (Q2 CY2026, K-IFRS, KRW tn)
Unweighted mean = 75.55%
OM_NVIDIA = 53,536 / 81,615 = 65.60% (Q1 FY2027, GAAP, USD m)
OM_TSMC = 766,603 / 1,270,381 = 60.34% (Q2 CY2026, TIFRS, NT$ m)
MMP vs NVIDIA = 75.55 − 65.60 = +9.96 pp (reported as +10.0 pp)
MMP vs TSMC = 75.55 − 60.34 = +15.21 pp (reported as +15.2 pp)
The mean is unweighted by design: weighting by revenue would let Samsung’s non-memory businesses dominate a memory metric. Arithmetic was verified computationally before publication.
Axis HBM4 Disclosure Index (HDI) — formula, v1.0. Four binary criteria, each weighted 0.25, scored solely from the supplier’s most recent public results disclosure. A criterion scores 1 only if the disclosure states the fact explicitly; inference from press coverage does not count. Baseline reading dated August 3, 2026.
Limitations, stated plainly.
- Reporting periods are not aligned. Micron’s fiscal Q3 covers March–May 2026; NVIDIA’s fiscal Q1 covers late January–April 2026; SK hynix, Samsung and TSMC report April–June 2026. Margins are therefore near-contemporaneous, not simultaneous. In a market moving this fast, a one-month offset is material.
- Samsung’s DS division is not a memory-only figure. It includes System LSI and Foundry. Samsung’s Memory Business margin, reported separately, would be higher. The DS figure understates memory profitability and is used because it is what Samsung discloses.
- Accounting standards differ. GAAP (Micron, NVIDIA), K-IFRS (SK hynix, Samsung), TIFRS (TSMC). Operating margin is comparable in structure but not identical in derivation.
- SK hynix and Samsung Q2 2026 results are preliminary and subject to change during independent audit.
- No HBM-specific revenue exists for two of the three suppliers. The MMP is a company- or division-level metric, not an HBM-segment metric. It is a proxy, and it is labelled as one.
- The HDI is a disclosure metric, not a capability ranking. It should never be cited as a measure of technology leadership or market share.
About This Dataset
Title: HBM Market Statistics 2026 — Supplier Financials, HBM4 Status, and Export-Control Parameters
Publisher: Axis Intelligence Research
Temporal coverage: December 2024 – August 2026
Spatial coverage: Global (suppliers headquartered in the United States, South Korea and Taiwan)
Format: CSV, UTF-8, one row per observation, full provenance columns
License: Creative Commons Attribution 4.0 International (CC BY 4.0). Free to share and adapt, including commercially, with attribution.
Suggested citation
- APA: Axis Intelligence Research. (2026, August 3). HBM market statistics 2026: Supplier margins, HBM4 ramp status, and the disclosure gap. Axis Intelligence. https://axis-intelligence.com/hbm-market-statistics/
- MLA: Axis Intelligence Research. “HBM Market Statistics 2026: Supplier Margins, HBM4 Ramp Status, and the Disclosure Gap.” Axis Intelligence, 3 Aug. 2026, axis-intelligence.com/hbm-market-statistics/.
- Chicago: Axis Intelligence Research. “HBM Market Statistics 2026: Supplier Margins, HBM4 Ramp Status, and the Disclosure Gap.” Axis Intelligence, August 3, 2026. https://axis-intelligence.com/hbm-market-statistics/.
Frequently Asked Questions
How many companies make HBM?
Three: SK hynix, Samsung Electronics and Micron Technology. All three shipped HBM4 in volume during the first half of calendar 2026.
What is the HBM market size in 2026?
No supplier discloses HBM revenue as a reported segment, so no audited market-size figure exists. Published market-size numbers are third-party models built from estimated bit shipments and pricing. Axis Intelligence Research publishes the suppliers’ reported financials instead, and identifies which figures are estimates.
Which company has the largest HBM market share?
Every published share figure is a research-firm estimate rather than a disclosed number, because none of the three suppliers reports HBM revenue separately. Axis Intelligence Research declines to restate share estimates as fact and instead tracks disclosure through the HBM4 Disclosure Index.
How much HBM4 revenue has Micron reported?
More than $1 billion, disclosed in its fiscal Q3 2026 earnings call prepared remarks on June 24, 2026. It is the only quantified HBM4 revenue figure any supplier has published.
What bandwidth does HBM4 deliver?
Up to 2 TB/s per stack, at transfer speeds up to 8 Gb/s across a 2,048-bit interface, per the JEDEC JESD270-4 standard published in April 2025. Independent channels per stack double from 16 to 32 versus HBM3.
Is HBM subject to U.S. export controls?
Yes. ECCN 3A090.c, effective December 2, 2024, controls HBM with memory bandwidth density above 2 GB/s/mm². BIS stated in the rule that all HBM stacks then in production exceed that threshold. A narrow carve-out, License Exception HBM, covers certain shipments below 3.3 GB/s/mm² under tracking conditions.
Why are DRAM and HBM prices rising so sharply in 2026?
Supply is structurally constrained. New capacity requires greenfield fabs with multi-year construction, permitting and power-infrastructure lead times, and each HBM generation consumes more wafer capacity per bit, reducing non-HBM DRAM supply. Micron reported sequential DRAM price increases in the low-60s percentage range in its fiscal Q3 2026 on bit shipments up only low single digits.
When will HBM supply catch up with demand?
Micron’s management stated in June 2026 that it has no line of sight to when memory supply catches up, while expecting gradual improvement in 2028. Samsung expects the market to remain undersupplied through the second half of 2026.
What is HBM4E and who has sampled it?
HBM4E is the next iteration after HBM4. Samsung says it shipped the industry’s first HBM4E samples to major customers; SK hynix completed HBM4E sample shipments in the first half of 2026; Micron expects HBM4E volume production in calendar 2027.
What is the Axis Memory Margin Premium?
A cross-source metric created by Axis Intelligence Research: the unweighted mean operating margin of the three HBM suppliers minus a reference company’s operating margin, using each firm’s most recently reported quarter. The baseline reading is +10.0 percentage points versus NVIDIA and +15.2 points versus TSMC. The formula and inputs are disclosed in the Methodology section.
Related Axis Intelligence Research: Semiconductor Statistics · AI Chip Market Share · GPU Shipment Statistics · AI Data Center Statistics · Nvidia Statistics · Samsung Statistics